Ny fanambarana momba ny tsiambaratelo: tena zava-dehibe ho anay ny tsiambaratelo. Mampanantena ny orinasantsika ny tsy hampahafantatra ny mombamomba anao manokana amin'ny fotoana iray izay misy ny fahazoan-dàlana mazava.
Model No.: NSO4GU3AB
Fitaovam-pitaterana: Ocean,Air,Express,Land
Payment Type: L/C,T/T,D/A
Incoterm: FOB,EXW,CIF
4GB 1600mhz 240-pin DDR3 Udimm
Tantaran'ny fanovana
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Fandaharana ny latabatra fampahalalana
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Description
Hengstar tsy voamarina DDR3 SDRAM SDRAM Dimms (Double Dange Domino Dram Dram Dram Dram Dual In-Line Modules) dia ambany hery, haino aman-jery haingam-pandeha haingam-pandeha izay mampiasa fitaovana SDRAM avo lenta. NS04Gu3AB dia 512m x 64-bit ny laharana roa 4GB 4GB DDR300 CL11 1.5V SDRAM tsy voaroaka ny vokatra DIMM, miorina amin'ny singa enina ambin'ny folo 256m x 8-bit. Ny SPD dia namboarina ho an'ny Jedec Standard Latency DDdr3-1600 Fahafatesana amin'ny 11-11-11 amin'ny 1.5v. Isaky ny 240-pin Dimm dia mampiasa rantsantanana misy rantsantanana. Ny Dimm SDRAM tsy voaroaka dia natao hampiasaina ho fahatsiarovana lehibe rehefa napetraka ao amin'ny rafitra toy ny PC sy ny toeram-piasana.
Toetoetra
power famatsiana: vdd = 1.52v (1.425v ka hatramin'ny 1.575v)
vddq = 1.5v (1.425v ka hatramin'ny 1.575v)
800mhz Fck ho an'ny 1600MB / sec / PIN
8 Banky anatiny mahaleo tena
programmable cas latency: 11, 10, 9, 8, 7, 6
pprogrammable addgitive latency: 0, cl - 2, na cl - 1 famantaranandro
8-bit mialoha mialoha
Burst Length: 8
bi-discoral Data Data Data Strobe
inavernal (self) calibration; Calibration anatiny amin'ny alàlan'ny ZQ PIN (RZQ: 240 Ohm ± 1%)
Fanginganana ny famaranana ny fampiasana ODT PIN
Fotoam-panavotana 7,8us ao ambany noho ny tatatra 85 ° C, 3.9us amin'ny 85 ° C <95 ° C
ASYNCHRONOUS RESET
Adjustabtable data-output tanjaka
fly-by topology
pcb: Height 1.18 "(30mm)
rohs dia mifehy sy halogen-maimaim-poana
Ny tarehimarika fanalahidy fototra
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Latabatra adiresy
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
Famaritana PIN
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Fanamarihana : Ny latabatra famaritana PIN eto ambany dia lisitra feno amin'ny basy rehetra azo atao ho an'ny modules DDR3 rehetra. Ny pins rehetra voatanisa dia mety tsy tohanana amin'ity module ity. Jereo ny fanendrena PIN amin'ny fampahalalana manokana amin'ity module ity.
Diagram underal
4GB, 512Mx64 Module (2rank of x8)
Modely Dimensions
Fijerena eo anoloana
Fijerena eo anoloana
Fanamarihana:
1.Ny refy rehetra dia ao amin'ny milimetatra (santimetatra); Max / Min na mahazatra (typle) izay misy azy.
2.Temerance amin'ny refy rehetra ± 0.15mm raha tsy voafaritra manokana.
3. Ny Dimensional Diagram dia natao ho an'ny fanondroana ihany.
Product Categories : Fitaovana maoderina Smartrial Smart
Ny fanambarana momba ny tsiambaratelo: tena zava-dehibe ho anay ny tsiambaratelo. Mampanantena ny orinasantsika ny tsy hampahafantatra ny mombamomba anao manokana amin'ny fotoana iray izay misy ny fahazoan-dàlana mazava.
Fenoy fampahalalana bebe kokoa mba hahafahanao mifampiresaka aminao haingana kokoa
Ny fanambarana momba ny tsiambaratelo: tena zava-dehibe ho anay ny tsiambaratelo. Mampanantena ny orinasantsika ny tsy hampahafantatra ny mombamomba anao manokana amin'ny fotoana iray izay misy ny fahazoan-dàlana mazava.